The present invention relates to integrated circuits. In particular, the present invention relates to adjusting parameters of dies of integrated circuit wafers.
Integrated circuits (ICs) are typically manufactured as part of wafers which include many dies. Each of these dies may be integrated circuits designed to meet certain predefined criterias. However, although the integrated circuit process attempts to meet these predefined criterias, there is typically a substantial distribution of the resulting ICs in meeting these criterias. An example of a predefined criteria is a predetermined speed at which the IC runs. If some of the ICs are out of the acceptable range of meeting the predetermined criteria, they are typically thrown away. For example, there may be 1,000-2,000 dies on a wafer. If a predefined criteria for these dies is a given operating speed of the die, then the wafer typically produces a percentage of dies that are too fast to be within the predefined operating speed as well as another percentage of dies that are too slow to be within the predefined operating speed. These dies that are either too fast or too slow are typically thrown away. Since the cost of the production of IC wafers are high, it is extremely expensive to throw away a substantial portion of the wafer.
It would be desirable to be able to use a higher percentage of dies on a wafer. The present invention addresses such a need.
The present invention relates to a system and method for compensating IC parameters. According to an embodiment of the present invention, a die of an IC wafer is coupled with a compensation circuit that classifies the die into various types. Examples of types include fast, typical, and slow. The assigned type may be used in a special oscillator that compensates for variations from the die to a predetermined criteria. The die is compared to the predetermined criteria. According to an embodiment of the present invention, a slow die directs a signal that moves through a relatively short path, a fast die directs a signal that moves through a relatively long path, and a typical die directs a signal that moves through a relatively medium length path in the compensation circuit. Accordingly, each die on a wafer may be coupled with a compensation circuit such that the compensation circuit selects a path of a circuit that adjusts the frequency produced by the dies to produce a batch of ICs that would meet the predetermined criteria for the vast majority of the dies. A large number of useable Ics would be produced by adjusting the frequency produced by the ICs which would conventionally not meet the predetermined criteria to a frequency that does meet the predetermined criteria.
A system according to an embodiment of the present invention for adjusting a frequency produced by an integrated circuit is presented. The system comprises an oscillator reflecting a first frequency of an integrated circuit. The system also includes a speed comparator coupled with the oscillator, the speed comparator being configured to classify the first frequency to a type. A frequency synthesizer coupled with the speed comparator is also included, wherein the frequency synthesizer produces a signal with a second frequency.
A method according to an embodiment for adjusting a frequency produced by an integrated circuit is also presented. The method comprises providing a first frequency of an integrated circuit. The method also includes classifying the first frequency to a type, and producing a signal with a second frequency.